Tags

19 pages

Blog

EDAcation: Hardware synthesis visualized

Meet the Devs - Nick

Interim YosysHQ LLM Policy

TaMaRa: Towards a Triple Modular Redundancy Pass for Yosys

Featured image of post TaMaRa: Towards a Triple Modular Redundancy Pass for Yosys

RISC-V Formal Verification Framework Extension for Synopsys VC Formal

Featured image of post RISC-V Formal Verification Framework Extension for Synopsys VC Formal

Sky130 SPICE, the KiCad way

Featured image of post Sky130 SPICE, the KiCad way

Logic Locking with Moosic

Featured image of post Logic Locking with Moosic

Solving a Sudoku with SBY and Formal Verification

Featured image of post Solving a Sudoku with SBY and Formal Verification

How I went from blinker to RISC-V in 3 months

Featured image of post How I went from blinker to RISC-V in 3 months

First gateware on the Colorlight 5A-75B board

Featured image of post First gateware on the Colorlight 5A-75B board