Memory inferencing overhaul.
Formal tristate support, x handling, optimising adders.
Teodor-Dumitru Ene presents his work on adder optimisations for the open source FPGA and ASIC tools
Co-simulation, new options for SBY, YosysHQ team is growing.
Yosys is the defacto synthesis tool for all the open source ASIC flows
Property Checking with SystemVerilog Assertions
Announcing a new series of app notes
YosysHQ is the new home for the team maintaining Yosys and related Open Source EDA projects