Open Source Silicon with Yosys

Yosys is the defacto synthesis tool for all the open source ASIC flows

Yosys is probably best known for providing synthesis for FPGA targets, but it’s a very flexible tool capable of a lot more.

OpenLane, SiliconCompiler and Coriolis2 are 3 examples of open source ASIC flows, which has been an active field of development over the last year.

We’re very happy to see our tools get used in the first Google sponsored tapeouts, helping to make the world’s first chips made with an open source PDK, and open source all the way down to the designs.

If you want to find out more about what happened in the world of open source silicon in 2021, you can see our CSO Matt Venn’s recent presentation for Hackaday Remoticon here:

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