The June release of Tabby CAD Suite is now available for download. Notable changes in this version include:

• The RISC-V Formal Verification Toolbox has gained a bus interface for checking that instructions relating to memory result in matching bus transactions, as well as some checks for the machine-mode CSRs required by the RISC-V privileged specification.

In other YosysHQ news:

• You might have seen Bruno Levy’s excellent introduction to RISCV on an FPGA. In our most recent blog post, guest author Bastian Löher shows how he followed the tutorial using Amaranth instead of Verilog.
• Nina & Matt will be attending the Free Silicon Conference in July.
• Matt will be attending the RISCV summit hardware track this Friday 9th June.

Happy June, The YosysHQ Team