Featured image of post Community Spotlight - sv2v

Community Spotlight - sv2v


Welcome to another community spotlight article where we shine a light on open source EDA projects. If you want to submit a project, please do so here.

sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005), with an emphasis on supporting synthesizable language constructs.

Zachary Snow’s Bio

zachary snow

I received my B.S. in computer science from Carnegie Mellon University in 2019. After graduating, I began working full-time as a software engineer in systematic trading. Since May, I have worked in systematic futures trading at the D. E. Shaw group.

What was your motivation in making sv2v?

While working as an undergraduate teaching assistant, Professor Dave Eckhardt introduced me to an open hardware research group that includes himself and Professor Ken Mai. Leveraging my prior studies in compilers, I was tasked with developing a tool to convert a RISC-V core written in SystemVerilog to Yosys-compatible Verilog. With help from others on the research team, we accomplished this goal prior to my graduation. Since then, I have continued to develop sv2v on a volunteer basis with the support of CMU and the larger open hardware community.

Why do you develop open source tools?

While I enjoy programming projects in general, I find working on open source tools especially rewarding. I appreciate that each improvement can benefit many users. I hope that my contributions can expand the viability of completely free and open source development in a space that is dominated by proprietary tools.

What are some of the challenges you face?

I have no formal training in electrical engineering or hardware development. Although I have gained experience since starting the project, I still depend on insight and advice from those who actually work on hardware and synthesis flows.

SystemVerilog is also a difficult language to work with due to its complexities and ambiguities. Even commercial toolchains vary in terms of feature support, strictness, and behavior. This can make it challenging to decide what language features to implement and how to translate them correctly.

What could the community do to support you?

I am always eager to receive more feedback. It is difficult to gauge interest in features or discover issues without users sharing their thoughts. The feedback I’ve received to date has been essential in making sv2v what it is today.

For those with experience with functional programming or compilers and an interest in SystemVerilog, there are a number of features and improvements that may be suitable for an outside collaborator. If you’re interested, please reach out!

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What is the best way for people to contact you?

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